1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of manufacturing the same.
2. Description of the Related Art
A MOS solid-state imaging element (image pickup element) has advantages of low power voltage, single power source and low cost. Recently, there is a rapid trend to make the solid-state imaging device which comprises a MOS solid-state imaging element fine. Therefore, Cu interconnect (wiring) which is appropriate for fine interconnect tends to be utilized more often than Al interconnect for interconnect in the solid-state imaging device (image pickup device).
In comparison with the Al interconnect, the Cu interconnect is resistant to electro-migration and can have a low profile due to manufacturing by a damascene process. Therefore, for the solid-state imaging device which comprises a microlens at the top layer, condensing light can be easy and sensitivity can be improved. On the other hand, for a logic circuit which is disposed in the solid-state imaging device, fining and integration can be achieved by utilizing the Cu interconnect. Accordingly, decreasing the area of the circuit and downsizing the module can be achieved.
However, when the Cu interconnect is utilized in the damascene process, there is a case that a part of large area such as a shielding layer is shaped as a recessed dish-shape which is called dishing caused by filling of Cu into a dug interlayer film. Therefore, it is difficult to utilize the Cu interconnect for a part of large area. Consequently, it is common to utilize the Cu interconnect for lower layer interconnect which requires fine processing and to utilize the Al interconnect for upper layer interconnect which design requirement is not so severe.
Document 1 (Jpn. Pat. Appln. KOKAI Publication No. 2001-298175) discloses a solid-state imaging device on which a variety of circuits are mounted which realizes high signal processing speed and integration with the imaging area (image pickup area) being low-risen for improving sensitivity and the peripheral circuits being multi-layered.
An image sensor of document 2 (Jpn. Pat. Appln. KOKAI Publication No. 2006-093687) has a shielding area which light shielding effect is superior by forming a metal layer pattern, a dummy pattern and an upper shielding film pattern.
In the solid-state imaging device on which the variety of circuits are mounted of document 1,  downsizing is performed by high speed signal processing and integration with the imaging area being low-risen for improving sensitivity and the peripheral circuits being multi-layered.
However, when the imaging area is low-risen and the peripheral circuits are multi-layered while utilizing the damascene Cu interconnect structure, the shielding layer position becomes high due to the multi-layering of the peripheral circuits and precise determining of a black reference level becomes difficult because inclined incident light enters into the optical black (OB) area which determines the zero level of a pixel.
Further, with a conventional solid-state imaging device, an invalid area (dummy area) needs to be enlarged in order to appropriately ensure the black reference level. Consequently, downsizing of the solid-state imaging device becomes difficult.
In document 2, it is not examined for entering of the inclined incident light to the OB area from the imaging area.